Processors are used for a very wide range of tasks, including, inter alia, mathematical calculations, database management, communications and the controlling of devices. In many cases, processors require a separate memory unit, for performing functions such as the storage of processing results or intermediate values, and/or from which to retrieve operation software and/or input data. A processor which controls the access to the memory is referred to as a “master”. The term master is also used to represent other units, not necessarily processors, which control access to a memory.
A variety of communication protocols have been defined for internal communication purposes, including data transfer between the processor and the memory unit. Some protocols were defined particularly for use in multi-processor configurations, wherein a plurality of processors can access a shared memory unit, such as through a bus, for example. Protocols for multiple processor applications sharing a common memory or other resource have rules governing which processor is allowed to access the memory unit and when. Such protocols generally define hand-shake methods, which are used to notify the processor when there is a problem in its communication with the memory unit. The main disadvantage of handshake protocols is their complexity, as in some applications, a simpler protocol is sufficient.
The Serial Peripheral Interface, henceforth SPI, is a simple synchronous data link protocol. SPI is designed for accessing one or more memory units by only a single master. Hence, SPI has no low layer provisions, such as hand-shake provisions, for verifying that instructions given were indeed performed. It also lacks error detection and correction provisions. Nevertheless, due to its simplicity, SPI enjoys the advantages of fast operation using a small number of communication lines. Consequently, SPI is a popular protocol for memory units associated with a single processor.
When, however, two processors require external memory units, each processor is required to have its own memory unit, regardless of how much memory space it requires and how often it accesses the memory unit.
One method of avoiding the necessity for separate memory units, is to have a first processor send access requests to a shared memory unit in a Low Pin Count (LPC) format that supports a bus-busy indication. In such a configuration, requests from the first processor are forwarded to the second processor which translates them into the SPI format and transfers them to the memory unit. It will be appreciated that this method requires the first processor supporting the LPC format and the second processor being configured to perform the format translation.
Another method of sharing a memory unit between processors is to perform a hardware handshake between two processors sharing the memory. This requires that the processors support the handshake protocol, and is complex when more than two processors are involved.
U.S. Pat. No. 5,603,055 to Evoy et al., dated Feb. 11, 1997, the disclosure of which is incorporated herein by reference, describes a method of sharing a ROM memory between a keyboard controller (i.e., processor) and a system processor. At initial boot-up, the system processor accesses the shared ROM to retrieve the system BIOS, and afterwards, the shared ROM is used by the keyboard controller. This method is unsuitable for applications wherein intermittent access to the memory is required by both processors.
U.S. Pat. No. 5,892,943 to Rockford, Dunnihoo and Wahler titled “Shared bios ROM warm boot”, the disclosure of which is incorporated herein by reference, describes the sharing of a memory unit between a host processor, which uses the memory unit for uploading the BIOS, and a keyboard controller. A logic circuitry connecting the host processor and the keyboard controller to the memory unit only allows the host processor to access the memory when the keyboard controller is disabled, such as when the computer is first turned on. When the host attempts to access the memory at a different time, the logic circuitry emulates a set of op-codes to the processor, causing it to access a copy of the BIOS located in the main memory of the host. While this may solve the problem of accessing the BIOS, it does not allow intermittent access to the memory unit. Furthermore, this solution requires a memory with a parallel access interface and is not suitable for a serial interface.
Other solutions with similar disadvantages are described in U.S. Pat. No. 5,999,476 to Dutton et al., in U.S. Pat. No. 5,794,054, to Le et al., patented Aug. 11, 1998, and in U.S. Pat. No. 6,154,838 to Le et al., patented Nov. 28, 2000, the disclosures of which are incorporated herein by reference.